Computer bus deadlock prevention
US4868741A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1986 |
| Grant date | Sep 19, 1989 |
| Priority date | — |
| Expiry date | Nov 25, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital computing system includes at least a first and a second bus with at least a first master connected to the first bus and a second master connected to the second bus. The first master is capable of requesting the second bus through the first bus and the second master is capable of requesting the first bus through the second bus. Central conversion means receives both requests and has circuitry for generating a response signal to the first bus when both requests come simultaneously. The first master receives the response signal and continues the cycle, but without continuing the request for the second bus. The cycle is completed as though the request had been completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.