Input/output bus for system which generates a new header parcel when an interrupted data block transfer between a computer and peripherals is resumed
US4868742A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 1988 |
| Grant date | Sep 19, 1989 |
| Priority date | — |
| Expiry date | Jun 9, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A communication bus (14) provides bidirectional data communication between a computer (12) and various peripheral units including input/output processors (18, 20) and a service processor (22). The computer includes a memory control unit (24) which is connected to a memory array (26). A central processor unit (30) is connected for data exchange with the memory control unit (24). Data blocks are transferred through the bus (14) and either originate or terminate at the memory array (26). A peripheral unit, such as the processor (18) transfers a data block by first transferring a header parcel (146) which defines an address, block length and type of function. This is transmitted to the memory control unit (24) which carries out the desired data transfer by sending or receiving sequential data parcels. An interrupt bus (16) connects each of the units of the computer system (10) including the processors (18, 20, 22) and the central processing unit (30). Any one of the units connected to the interrupt bus ( 16) can interrupt any of the other units. The interrupt process comprises sending an interrupt vector through interrupt lines (66). At the receiving unit the interrupt is identified an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.