Speed enhancement for multipliers using minimal path algorithm
US4868778A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 14, 1987 |
| Grant date | Sep 19, 1989 |
| Priority date | — |
| Expiry date | Dec 14, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3896
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A binary multiplier architecture which multiplies signed and unsigned operands as unsigned numbers and adds a correction factor which is the two's complement of the other operand if the operand is signed. The multiplier architecture performs two's complement multiplication when the multiplier has 1's in more than half of its bits and performs unsigned binary multiplication by adding only shifted multiplicand vectors as a function of the multiplier all other times. Two's complement multiplication is performed by adding a multiplicand and a multiplier to two's complemented shifted multiplicand vectors as a function of the two's complement of the multiplier. To reduce the number of additions necessary, portions of the operands are merged with the shifted complemented vectors prior to addition to the shifted vectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.