Memory chip array with inverting and non-inverting address drivers
US4870619A · kind A · utility
13Cited by
2References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 14, 1986 |
| Grant date | Sep 26, 1989 |
| Priority date | — |
| Expiry date | Oct 14, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory arrangement is comprised of a plurality of memory chips, and address and control lines connected to the chips. In order to minimize the effect of interference of signals from the address lines on the control lines, the address lines coupled to a portion of the chips carry address signals in inverted form, as compared with the address signals applied to the remainder of the chips, whereby interference signals of opposite polarity are induced in the control lines and cancel each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.