Dynamic random access memory device with internal refresh
US4870620A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1988 |
| Grant date | Sep 26, 1989 |
| Priority date | — |
| Expiry date | Jan 5, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The switching circuit 4 receives external address signals EXT. A.sub.0 to A.sub.8 or output signals Q.sub.0 to Q.sub.8 from the refresh counter 2 and selects either of these signals in response to the clock signals .phi..sub.2 and .phi..sub.2 to apply the same to the address buffer 1. A plurality of N type field effect transistors, which operate in response to the clock signal .phi..sub.3, such as transistors 540, 54 and 548 are connected between each of the inputs of the switching circuit 4 for receiving the external address signals EXT. A.sub.0 to A.sub.8 and the ground V.sub.ss. Referring to the i-th circuit portion, before the switching circuit 4 applies a signal Q.sub.i from the refresh counter 2 to the address buffer 1, the transistor 54 turns on in response to the clock signal .phi..sub.3 and brings the input of the address buffer 1 to the voltage level of the ground V.sub.ss. When the switching circuit 4 is switched, the signal from the refresh counter 2 is correctly applied to the address buffer 1. Therefore, malfunctions of the address buffer 1 can be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.