Variable frequency rate receiver
US4870660A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 28, 1987 |
| Grant date | Sep 26, 1989 |
| Priority date | — |
| Expiry date | Dec 28, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2273
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A variable data rate receiver is provided which employs a novel phase locked loop (PLL) of the type employing a data detection loop and a tracking loop. The data detection loop is initially not coupled to the input of the voltage controlled oscillator in the tracking loop of the PLL, but is separated by an electronic switch. A phase lock detection circuit is provided which is coupled to the data detection loop and to the tracking loop for detecting the difference in the voltage error signals in the data detection loop and the tracking loop. When this error signal indicates that the tracking loop is locked on to the carrier signal the electronic switch is closed completing the phase locked loop circuit after lock on of the carrier is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.