Contention mechanism for communication networks
US4872163A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Dec 22, 1988 |
| Grant date | Oct 3, 1989 |
| Priority date | — |
| Expiry date | Dec 22, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/44
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A contention mechanism is disclosed for a communication network that provides perfect scheduling to avoid collisions between packets from a cluster of M circuit boards connected to a communications bus. The contention mechanism includes a 2-phase contention procedure comprising a first phase priority contention phase, where boards with a highest priority and a real data packet to transmit proceed into a second contention phase, where a pointer is used to declare one of the remaining priority phase circuit boards as the overall winner to transmit its packet during a subsequent packet period. When no circuit board has a packet to transmit, all M circuit boards are declared as winners of the first priority phase, and a board is declared the winner on a distributed basis to transmit a "dead-space" packet over the bus. The real and dead-space packets can also be encoded and/or include a parity bit to ensure signal transitions sufficient to maintain a duty cycle required by A-C coupled devices connected in the network and also provide fault isolation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.