Integrated circuit with memory self-test
US4872168A · kind A · utility
50Cited by
11References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1986 |
| Grant date | Oct 3, 1989 |
| Priority date | — |
| Expiry date | Oct 2, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array included with logic circuitry on an integrated circuit is tested by a technique that reads and writes a specified sequence of test bits into a given memory word before progressing to the next word. A checkerboard pattern of 1's and 0's is written into the physical memory locations. This provides for an improved worst-case test while allowing case of implementation for the test circuitry. The test results from a comparator circuit may be compressed to provide one (or a few) test flags indicating whether the memory passed the test, requiring a minimal number of test pads or terminals for the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.