Retention means for chip carrier sockets
US4872845A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 1988 |
| Grant date | Oct 10, 1989 |
| Priority date | — |
| Expiry date | May 6, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K7/1007
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Chip carrier sockets (2) have terminals (4) provided therein, the terminals (4) comprising leg portions (34) with first resilient arms (18) and second resilient arms (20) pivotally attached thereto. The first resilient arms (18) have contact surfaces (26) provided on free end sections (22) thereof. The contact surfaces (26) are provided to electrically engage leads (6) of the chip carrier (8). A cover (12) is provided to cooperate with the chip carrier and to act as a protective handler for the chip carrier. Retention means are positioned on the chip carrier socket (2) to cooperate with the cover (12), thereby providing the contact force required to insure that a positive electrical connection is effected between the leads (6) and the terminals (4). The resilient configuration of the retention means insures that the retention means will not fail under normal stresses associated therewith.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.