Solid state monolithic switching device
US4873563A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 1988 |
| Grant date | Oct 10, 1989 |
| Priority date | — |
| Expiry date | May 2, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A monolithic switching array integrated with control logic on a dielectrically isolated monolithic substrate is provided wherein individual components are constructed in abutment with the oxide walls of the dielectrically isolated wells to form a diffusion/wall interface. As a consequence, area of the wells can be optimally used, and undesired electric fields around the components are minimized, thus allowing for smaller overall chip dimensions as compared with comparable prior art dielectric isolation (d.i.) or junction isolated construction techniques. Moreover, d.i. construction eliminates undesired parasitic devices in a monolithic circuit and allows for improved system accuracy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.