Semiconductor chip carrier system
US4873615A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 23, 1987 |
| Grant date | Oct 10, 1989 |
| Priority date | — |
| Expiry date | Sep 23, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit semiconductor chip carrier system (10) which provides reliable interconnection of one or more semiconductor chips (13) to external circuitry in environments of variable temperature and stress. The system (10) includes a housing (11), one or more semiconductor chips (13) mounted on a substrate (12), and a plurality of electrical terminals (36) which extend through one or more walls (21, 22, 23, 24) of the housing (11). Each terminal (36) having an inner resilient portion (36b) which is adapted to be electrically connected to a contact pad (32) which is in electrical engagement with a semiconductor chip (13) on the substrate (12). The inner resilient portions (36b) being directly connected to the pads (32) in such a manner so that as the substrate (12) expands and contracts according to temperature variations, the inner resilient portions (36b) move accordingly, thereby eliminating harmful stresses which results in "bi-metal effect". A non-conductive, flexible, electrical interconnection member (76) is also provided for electrically connecting the semiconductor chips (13) of the substrate (12) to a plurality of terminals (36). The interconnection member (76) is …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.