Instruction processing unit for computer
US4873629A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1987 |
| Grant date | Oct 10, 1989 |
| Priority date | — |
| Expiry date | Dec 15, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3822
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer (20) is configured for optimizing the processing rate of instructions and the throughput of data. The computer (20) includes a main memory (99), a memory control unit (22), a physical cache unit (100), and a central processor (156). A instruction processing unit (126) is included within the central processor (156). The function of the instruction processing unit (126) is to decode instructions and produce instruction execution commands or directing the execution of the instructions within the central processor (156). Instructions are transferred from the main memory (99) into a register (180) where the address fields of the instructions are decoded to produce a cracked instruction and these instructions are stored in a logical instruction cache (210). As the cracked instructions are selected they are transferred to an output buffer and decoder (214) where the remaining fields of the instructions are decoded to produce instruction execution commands. The instructions in the cache (210) are stored at logical rather than at physical addresses. The cache (210) further can operate at double the rate of a basic clock period for the computer (20) such that a branch instruction …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.