Dual storage cell memory including data transfer circuits
US4873665A · kind A · utility
30Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1988 |
| Grant date | Oct 10, 1989 |
| Priority date | — |
| Expiry date | Jun 7, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/287
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.