Method and apparatus for effectively doubling the operational speed of selected digital circuits
US4873704A · kind A · utility
1Cited by
5References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 9, 1988 |
| Grant date | Oct 10, 1989 |
| Priority date | — |
| Expiry date | May 9, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/00006
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for effectively doubling the operational speed of certain digital circuit designs. In particular, a digital clock operating at a first frequency is utilized to effectively drive TTL shift registers at twice the frequency of the digital clock. This effective doubling of the clock speed is achieved without the necessity of resorting to expensive and high power consumption circuit designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.