Process of packaging a semiconductor device with reduced stress forces
US4874722A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1988 |
| Grant date | Oct 17, 1989 |
| Priority date | — |
| Expiry date | Apr 28, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/53174
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of producing a cavity package semiconductor device is disclosed. The method includes providing a bar pad having a plurality of bar pad straps, each strap extending outwardly from the outer edge of the bar pad and spaced about the edge of the bar pad; mounting integrated circuits having bond pads on the bar pad; molding a packing material onto a central portion of lead fingers and the bar straps to grip and surround each lead finger with package material, with a portion of each lead finger extending externally from the ring at both the exterior and interior thereof and to secure the bar pad straps therein; electrically coupling the bond pads to the portion of desired ones of the lead fingers extending toward the interior of the ring; and enclosing both ends of the ring to provide a cavity in the ring to suspend a bar pad with the integrated circuit thereon within the cavity with the bar pad straps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.