Neuromorphic learning networks
US4874963A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 11, 1988 |
| Grant date | Oct 17, 1989 |
| Priority date | — |
| Expiry date | Feb 11, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A neuron network which achieves learning by means of a modified Boltzmann algorithm. The network may comprise interconnected input, hidden and output layers of neurons, the neurons being "on-off" or threshold electronic devices which are symmetrically connected by means of adjustable-weight synapse pairs. The synapses comprise the source-drain circuits of a plurality of paralleled FETs which differ in resistance or conductance in a binary sequence. The synapses are controlled by the output of an Up-Down counter, the reading of which is controlled by the results of a correlation of the states of the two neurons connected by the synapse pairs following the application of a set of plus and minus training signals to selected neurons of said network. A noise generator comprising a thermal noise source is provided for each neuron for the purpose of simulated annealing of the network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.