Fixed-point multiplier-accumulator architecture
US4876660A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 1987 |
| Grant date | Oct 24, 1989 |
| Priority date | — |
| Expiry date | Apr 6, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3868
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit multiplier-accumulator architecture includes an M-bit wide register for inputting an X operand and an N-bit wide input register for inputting a Y operand to a multiplier. The multiplier can selectably multiply or concatenate the operands to produce a binary product in the form of a first array of M+N parallel bits. A binary adder adds the binary product to a second array of M+N+P+1 parallel bits and outputs the sum as a Z result in the form of a third array of M+N+P+1 parallel bits. The Z result is stored in a selected one of two accumulators. A feedback path is provided to output selected accumulator contents to the adder as the second binary array of M+N+P+1 bits. Output ports are provided for outputting a selected portion of the accumulator contents. Preferably, the output ports can output the entire M+N+P bits in parallel, as well as any selected portion thereof. Overflow logic can be provided which determines from the (M+ n+P+1)th bit whether an overflow has occurred in the M+N+P bit result. A format adjust circuit is provided between the accumulators and the output ports for shifting the entire output accumulator contents a predetermined number of bits w…
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