Cascade FET logic circuits
US4877976A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Oct 13, 1988 |
| Grant date | Oct 31, 1989 |
| Priority date | — |
| Expiry date | Oct 13, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09403
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A group III-V digital logic circuit which includes either at least two enhancement type metal semiconductor field effect transistors and one load element or two first type field effect transistors having a first threshold voltage and two second type field effect transistors having a second threshold voltage, for providing a logic operation. The second threshold voltage is less than zero and is less than the first threshold voltage. The group III-V digital logic circuit can be formed as an integrated circuit on, in particular, a GaAs substrate. The field effect transistor can be either a metal semiconductor field effect transistor or a junction field effect transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.