Single transistor cell for electrically-erasable programmable read-only memory and array thereof
US4878101A · kind A · utility
11Cited by
9References
3Claims
0Family size
Inventors
Key dates
| Filing date | Dec 29, 1986 |
| Grant date | Oct 31, 1989 |
| Priority date | — |
| Expiry date | Dec 29, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single transistor EEPROM cell utilizes a tunneling oxide erase mechanism in which the tunneling oxide overlies a portion of the channel region. In addition, an array of single transistor EEPROM cells having a layout which provides convenient byte-at-a-time erase and program operation is disclosed. Two bytes of the array along adjacent rows share a common source, which also forms the source of a pair of erase select transistors, one for each byte. The word lines/control gates of the two bytes form the gates of the two erase select transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.