Method and apparatus for image processing with fed-back error correction
US4878125A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1987 |
| Grant date | Oct 31, 1989 |
| Priority date | — |
| Expiry date | Dec 31, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/10008
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
There is an image processing apparatus for digitally processing an image. This apparatus comprises: a binarization circuit to binarize image data by a predetermined threshold value; a processor to correct errors generated in binarization; a first detector to detect an edge direction of the image from the image data; and a second detector to detect an edge quantum of the image from the image data. The process corrects the error data in accordance with the edge direction detected by the first detector or the edge quantum detected by the second detector. The errors to be corrected by the processor are the errors between the output concentration data after the binarization and the image concentration data. The processor adds weight coefficients to the error data in a predetermined range stored in a memory and then adds the weighted error data to image data to be newly binarized. The sum of the weight coefficients which are used in the weighting process is set to "1". With this apparatus, a high quality apparatus can be reproduced with a high fidelity from an original including many edges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.