Static ram with common data line equalization
US4878198A · kind A · utility
6Cited by
7References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 25, 1988 |
| Grant date | Oct 31, 1989 |
| Priority date | — |
| Expiry date | Jan 25, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory having a plurality of pairs of common data out lines. A plurality of bit line pairs are coupled to each pair of common data out lines. The common data out lines are automatically equalized at the end of each memory access cycle, and the accessed bit lines are automatically equalized at the end of each write cycle. Thus, the process of equalizing the common data out lines is removed from the critical timing path for accessing the memory, which eliminates one of the primary problems in the use of address transition detection in static memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.