Switching array with concurrent marking capability
US4879551A · kind A · utility
61Cited by
2References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1985 |
| Grant date | Nov 7, 1989 |
| Priority date | — |
| Expiry date | Apr 26, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q3/521
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A cross-point switching array in which each cross-point of the array is controlled by the output of a first memory. Each first memory is associated with a second memory. The second memories can be sequentially set by a single controller while the cross-point connections are maintained according to the first memories. The contents of all second memories are concurrently loaded into the associated first memories to simultaneously reconfigure the cross-point array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.