Memory device having valid bit storage units to be reset in batch
US4879687A · kind A · utility
30Cited by
3References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1987 |
| Grant date | Nov 7, 1989 |
| Priority date | — |
| Expiry date | Jun 8, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes plural word data storing rows. Each word data storing row is composed of a plurality of data bit cells for storing the word data, and a valid bit cell for indicating the validity of data. The valid bit cell has a reset circuit composed of FETs, and the reset circuits are connected to one reset line. By applying a reset signal to one reset line, plural valid bit cells are reset as a batch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.