Jitter tolerant circuit for dual rail data
US4879730A · kind A · utility
0Cited by
4References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 1988 |
| Grant date | Nov 7, 1989 |
| Priority date | — |
| Expiry date | May 31, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/242
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A retiming circuit is provided which accurately converts half-width dual rail data with up to one unit interval of jitter with respect to the data clock, into full-width data. The circuit is comprised of D-flip-flops and associated logic elements which capture and hold a data pulse until the captured data pulse can be accurately transferred to the next circuit stage by a positive clock transition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.