Sealing and stress relief layers and use thereof
US4880684A · kind A · utility
67Cited by
9References
60Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1988 |
| Grant date | Nov 14, 1989 |
| Priority date | — |
| Expiry date | Mar 11, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/31681
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Sealing and stress relief are provided to a low-fracture strength glass-ceramic substrate. Hermeticity is addressed through the use of capture pads in alignment with vias and through polymer overlays with interconnection between the underlying via or pad metallurgy and the device, chip, wire or pin bonded to the surface of the layer. Multilevel structures are taught along with a self-aligned sealing and wiring process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.