Computer system architecture employing cache data line move-out queue buffer
US4881163A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1986 |
| Grant date | Nov 14, 1989 |
| Priority date | — |
| Expiry date | Sep 19, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A queue buffer used for the controlled buffering and transferal of data between a cache memory of a central processor unit and a mainstore memory unit. The queue buffer of the present invention preferably includes a buffer memory for the queued storage of data and a controller for directing the nominally immediate acceptance and storage of data received direct from a cache memory and for the nominally systematic background transfer of data from the queue buffer to the mainstore memory unit. This nominal prioritization of memory transfers with respect to the queue buffer memory allows data move-in requests requiring data from the main storage unit to proceed while required move-out data is moved from a cache memory immediately to the buffer queue memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.