Debugging microprocessor
US4881228A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 1987 |
| Grant date | Nov 14, 1989 |
| Priority date | — |
| Expiry date | Oct 29, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A debugging processor includes a bus control unit for transmitting and receiving data to and from an external, an instruction execution unit receiving an instruction code from the bus control unit for executing the given instruction, and an interrupt control unit for notifying the instruction execution unit of an interrupt request. The debugging processor also comprises a debug interrupt response control unit having a priority higher than that of the interrupt control unit and having a fixed branch destination address. This debug interrupt response control unit operates to generate to the external a debug interrupt response signal which becomes active during a period of save operation for an internal information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.