Method and apparatus for error correction
US4881232A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 1988 |
| Grant date | Nov 14, 1989 |
| Priority date | — |
| Expiry date | Feb 5, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error-correcting method and apparatus for a block of data provided with an error-correcting parity for error correction and an error-checking parity that can be used to generate a syndrome for error-checking, in which error correction is carried out by the use of the error-correcting parity and then an error check is carried out by the use of the error-checking parity thereby to increase the reliability of the error-checking data, wherein error information produced by the error-correction process using the error-correcting parity is utilized to correct the syndrome used in the error-checking process, so as to execute the respective operations in parallel and reduce the required data processing time or through-put.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.