Process for the production of electrical isolation zones in a CMOS integrated circuit
US4882291A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 16, 1988 |
| Grant date | Nov 21, 1989 |
| Priority date | — |
| Expiry date | Aug 16, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/978
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The CMOS circuit has n regions (12a) and p regions (28) formed in a silicon substrate (2b). First and second masks are produced on substrate (2b), respectively having first (8a) and second (15) patterns masking the p regions and n regions. These masks can be selectively etched. The first and second patterns define between them the location of the isolation trenches (18) to be produced. The substrate is etched through the masks to form the trenches and simultaneously etching takes place of the first patterns and the underlying substrate in order to form in the upper part of the trenches inclined sides in contact with the p regions, in such a way that the section of trench (18) widens towards the upper surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.