Process for forming an epitaxial layer having portions of different thicknesses
US4882294A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 17, 1988 |
| Grant date | Nov 21, 1989 |
| Priority date | — |
| Expiry date | Aug 17, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/15
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device uses a silicon chip having an epitaxial layer which has two portions of different thicknesses in which are formed separate junction transistors of different characteristics. In the growth of the epitaxial layer there is first formed on the front surface of the chip a localized sacrificial silicon dioxide layer removable in situ by baking in a reducing atmosphere. Then an epitaxial layer is grown by a first epitaxial deposition phase selectively over only the silicon dioxide free regions of the front surface of the chip. The sacrificial silicon dioxide layer is then removed in situ by baking in hydrogen. There is then resumed blanket growth of the epitaxial layer by a second epitaxial deposition phase. In the resulting chip, a large geometry junction transistor of relatively low switching speed and moderately high breakdown voltage (compared to 12 volts) is formed in the thicker epitaxial portion and a small geometry junction transistor of high switching speed and lower breakdown voltage is formed in the thinner epitaxial portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.