FIFO memory including dynamic memory elements
US4882710A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1987 |
| Grant date | Nov 21, 1989 |
| Priority date | — |
| Expiry date | Sep 9, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A FIFO memory is provided with individual arrays of dynamic memory cells and includes a dedicated write line buffer memory and a dedicated read line buffer memory operably connected thereto. First and second line buffer memories are also provided in conjunction with the write line buffer memory and the read line buffer memory so as to permit a faster response to the input and output of data with respect to the FIFO memory. Data may be alternately written into either one of the line buffer memories as a lead-in to the subsequent writing of data in the dynamic memory arrays via the write line buffer memory. Data read out from the other line buffer memory may occur simultaneously. The FIFO memory may serve as a video data frame memory for storing a frame of a video screen image. Where video data is continuously written into the FIFO memory, either the preceding video data frame or the current video data frame that is being written is subject to read out depending on the timing of a read reset signal relative to the last write reset signal. The write line buffer memory and the read line buffer memory are operable independently of each other, and may have simultaneous cycle times withou…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.