Non-volatile memory system
US4882711A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 3, 1988 |
| Grant date | Nov 21, 1989 |
| Priority date | — |
| Expiry date | Feb 3, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system comprising PA0 a first, volatile memory (6) having a plurality of memory cells; at least one second, non-volatile memory (E.sub.l E.sub.n) having a plurality of memory cells; power-down means (12) for sensing when power is withdrawn from the first memory and for transferring in response thereto contents of the cells of the first memory to the cells of the second memory; and power-up means (10) for sensing when power is applied to the first memory and for transferring in response thereto contents of the cells of the second memory to the cells of the first memory, is characterised by a plurality of said second, non-volatile memories and further comprising a register (8) for holding an indication of which of the second memories is to be used for transfer by at least the power-down means.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.