Paging controller having a multiplex bus arrangement
US4882729A · kind A · utility
6Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1988 |
| Grant date | Nov 21, 1989 |
| Priority date | — |
| Expiry date | Aug 7, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W88/185
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A paging controller for a paging communication system exchanges information by a global multiplexed bus arrangement. The bus arrangement permits voice, data and control information to be exchanged between a common memory and a plurality of I/O modules in a common communication bus. The timing signals of the bus arrangement including the I/O modules are synchronized to expeditiously exchange information among the modules. In operation, each module has a preassigned address representative of a sequence number in a predetermined succession order to permit each module to access the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.