Mesfet latch circuit
US4883985A · kind A · utility
7Cited by
18References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1987 |
| Grant date | Nov 28, 1989 |
| Priority date | — |
| Expiry date | Oct 28, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356069
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An FET circuit suitable for a latch has a pair of inverters. The input stage FET of each of the inverters is connected such that the gate electrode thereof is connected to receive an output signal of the FET of the other inverter through a circuit having an FET and at least a diode. The sources of the input stage FETs are connected to a common connection point, and a current source arrangement such as a resistor is connected between the common connection point and a power supply terminal. The circuit provides an extended allowable range of the effective threshold voltage V.sub.T and has small power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.