Antibounce circuit for digital circuits
US4883993A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 1988 |
| Grant date | Nov 28, 1989 |
| Priority date | — |
| Expiry date | Dec 2, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1252
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The antibounce circuit comprises: PA1 (a) a first flip-flop constituted by a first and a second NAND gate (10, 12) having their respective outputs connected to one of the inputs of the other gate, the free input of the first gate being the input for said digital signal; PA1 (b) a second flip-flop constituted by a third and fourth NAND gate (14, 16) having their respective outputs connected to one of the inputs of the other gate, the free input of the third gate being connected to the output of the first gate; PA1 (c) a non-inverting delay circuit (20, 22, 24) connecting the output of the third gate to the free input of the second gate; PA1 (d) a first inverter connecting the output of the delay circuit to the free input of the fourth gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.