Double metal HCMOS compacted array

US4884118A · kind A · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Alex Chi-Ming Hui · Mill Valley, US
• Anthony Wong · Cupertino, US
• Conrad J. Dell'Oca · Mill Valley, US
• Daniel Wong · San Jose, US
• Roger To-Hoi Szeto · Shanghai, CN

Key dates

• Filing date: Feb 12, 1988
• Grant date: Nov 28, 1989
• Expiry date: Feb 12, 2008

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/907

Abstract

A gate array is provided in which active areas within the substrate are arranged in alternating columns of opposite conductivity type and symmetrical about the center lines through each column so that CMOS devices can be advantageously formed by allocating only small increments of active area to metal routing. The substrate and well taps are also symmetrical about the column center line. The active area symmetry allows p-channel and n-channel transistors to be combined where the p-channel transistor is on either the right or left, thus increasing the flexibility in placing the elements within the integrated circuit chip.