Memory array unit for computer
US4884191A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 1989 |
| Grant date | Nov 28, 1989 |
| Priority date | — |
| Expiry date | Mar 24, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The computer (10) includes a memory control unit (12), a central processing unit (14) and a memory array unit (16). A plurality of memory array planes (36, 38, 40 and 42) are included within the memory array unit (16). A latch (82) receives write data from the memory control unit (12) through a bus (26). Address and control information is transferred from the memory control unit (12) to timing and address circuits (28, 30, 32, 34). The write data is transferred from the latch (82) into a selected one of the memory array planes (36, 38, 40, 42). For each of the memory array planes (36, 38, 40, 42) there is provided a respective read latch (60, 62, 64, 66) for receiving read data. The ouputs of the memory array planes are not connected in common. The ouputs to read latches (60, 62, 64,66) are connected in common through a bus (76) for transferring read data through the data bus (26) back to the memory control unit (12). The memory array unit (16) provides enhanced speed of operation for the computer (10) while permitting refresh interrupts to occur without loss of read or write data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.