Single cycle processor/cache interface
US4884198A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1986 |
| Grant date | Nov 28, 1989 |
| Priority date | — |
| Expiry date | Dec 18, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0877
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved interface between a processor and an external cache system, having particular application for use in high speed computer systems. A cache memory for storing frequently accessed data is coupled to a cache address register (CAR). A processor generates addresses which correspond to locations of desired data in the cache, and provides these addresses to the CAR. Upon the receipt of a clock signal, the CAR couples the address to the cache memory. The processor includes a data register for receiving accessed cache data over a data bus. Data is latched into the register upon the receipt of a clock signal. Due to inherent delays associated with digital logic comprising the processor, clock signals provided by an external clock are received by the CAR prior to their receipt by the processor's data register. This delay (a fraction of a clock cycle) provides additional time to access the cache memory before the data is expected on the data bus. The CAR is fabricated out of a technology that allows it to drive the address to the large capacitive load of the cache memory in much less time than the processor itself could drive such a load. Thus, due to this buffering capability of th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.