Dynamic RAM refresh circuit with DMA access
US4884234A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1987 |
| Grant date | Nov 28, 1989 |
| Priority date | — |
| Expiry date | Jun 29, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory controller chip associated with a remote DMA device, a multispeed microprocessor and a DRAM memory requiring refreshing periodically includes refresh circuits for generating refresh signals for controlling refreshing of the memory during transparent and contention refresh operations. When a conflict occurs between the DMA device requesting access to the memory and the occurrence of a transparent refresh operation, control signals are generated to allow the memory to be refreshed prior to the time the DMA device is given access to the memory, thereby eliminating the need for a contention refresh operation. Control signals are also generated in accordance with the speed of the microprocessor for synchronizing the operation of the microprocessor with the operation of the DMA device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.