Patent · US Expired

Transistor arrangement with an output transistor

US4886985A · kind A · utility

4Cited by

4References

4Claims

0Family size

Assignee

Robert Bosch GmbH · DE

Inventors

Peter Flohrs · Reutlingen, DE
Klaus Heyke · Reutlingen, DE
Hartmut Michel
Ulrich Nelle · Mössingen, DE

Key dates

Filing date	Dec 23, 1988
Grant date	Dec 12, 1989
Priority date	—
Expiry date	Dec 23, 2008

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/63
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A transistor arrangement, particularly for the fast switching of inductive loads, includes a driving first transistor and a power output second transistor (T1, T2) interconnected as a Darlington pair having a base terminal, an emitter terminal and a collector terminal. A third transistor (T3) has its collector connected to the base of the first transistor (T1) and its emitter connected to the emitter terminal (E). A fourth transistor (T4) of a conductivity type opposite to that of the first, second and third transistors has its base connected to the collector terminal, its emitter connected to the base terminal, and its collector connected to the base of the third transistor (T3). This structure is particularly suited for a monolithic integration.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.