Dual level polysilicon single transistor-capacitor memory array

US4887135A · kind A · utility

Assignee

• American Telephone and Telegraph Company, AT&T Bell Laboratories · US

Inventors

• Glen T. Cheney · Allentown, US
• Howard C. Kirsch · Eagle, US
• James T. Nelson · Coopersburg, US
• James H. Stefany · Phillipsburg, US

Key dates

• Filing date: Jan 24, 1985
• Grant date: Dec 12, 1989
• Expiry date: Jan 24, 2005

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/30

Abstract

A self-aligned one transistor-capacitor memory cell is provided which uses an n-channel MOS transistor having separate drain and source regions with a first level polysilicon conductor coupled to the top plate of the capacitor and separate second level polysilicon conductors coupled to the gate and drain of the transistor. A reduction in a dimension of the memory cell is acheived compared to a similar memory cell which uses only one level of conductors.