Equalizer for digital transmission systems
US4887278A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 23, 1987 |
| Grant date | Dec 12, 1989 |
| Priority date | — |
| Expiry date | Sep 23, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/06
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A post-equalizer and pre-equalizer circuit for use in communicating between nodes in a pulse amplitude modulated digital communication system is described. The post-equalizer circuit comprises a first variable zero circuit, a second variable circuit, and a gain shaper circuit wherein the gain and frequency location of the zeros in the zero circuits combined with the gain of the gain shaping circuit are simultaneously controlled by a control circuit which generates a control voltage which is a monotonically increasing function of cable loss. The control voltage generates a signal equal to the difference between the equalized signal and the original transmitted signal which is used to vary the resistance of voltage variable resistors in the form of FET's in each of the zero circuits and gain shaper circuits. If the cable loss is above a predetermined value, a pre-equalizer circuit is switched into the transmit path of the communication system and provides a gain, zero and pole at predetermined frequencies which pre-compensates for the extra loss incurred in transmission over length greater than can be equalized by the post-equalizer. Additionally, a bi-quad ACE circuit is described w…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.