Semiconductor dynamic memory device
US4888631A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 1988 |
| Grant date | Dec 19, 1989 |
| Priority date | — |
| Expiry date | Nov 3, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
Abstract
A semiconductor IC element is three-dimensionally structured with a first active layer formed on a single crystalline silicon substrate and a second active layer formed by melting polycrystalline silicon by irradiation on an insulative layer which electrically insulates it from the first layer. Each active layer is comprised of single crystalline areas where transistors may be formed and separation areas which insulate them. PMOS, NMOS or CMOS field effective transistors are formed on these active element areas. A test circuit for testing the originally intended functions of the element as well as its redundant circuits may be formed on these layers. Throughholes are provided to connect the vertically separated active layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.