Memory control system
US4888687A · kind A · utility
69Cited by
7References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 1987 |
| Grant date | Dec 19, 1989 |
| Priority date | — |
| Expiry date | May 4, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0661
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for controlling the addressing of a memory on a predetermined multi-megabyte decode boundary. An address shifter is coupled between CPU address lines and backplane area bussed address lines. The address shifter is controlled in accordance with the control signal determined by the memory array of largest capacity of all memory arrays. The control signal has different states to control the address shifter to couple different address bit patterns therethrough to the backplane area address bus as a function of the selected control signal state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.