Apparatus and method for improving cache access throughput in pipelined processors
US4888689A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 1986 |
| Grant date | Dec 19, 1989 |
| Priority date | — |
| Expiry date | Oct 17, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/383
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for use in improving cache storage unit utilization during an interlock of an instruction pipeline generates a control signal during one cycle of the interlock if the interlocked instruction may require storage unit management work. In response to the control signal, selector control logic in the storage unit generates a priority signal indicating the interlocked instruction for selection by the storage unit for processing. In response to the control signal and the priority signal, the cache management logic is used during the interlock on the interlocked instruction to prepare for supplying needed data when the interlock is released.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.