Arrangement for bit-parallel addition of binary numbers with carry-save overflow correction

US4888723A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Erik De Man · Hersbruck, DE
• Tobias Noll · Neckartailfingen, DE

Key dates

• Filing date: Jun 10, 1987
• Grant date: Dec 19, 1989
• Expiry date: Jun 10, 2007

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F7/4991
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A series of adders (AD.sub.i) with inputs for binary number bits of the same significance, which output intermediate sum and carry words that are combined to form sum words, are provided for the bit-parallel addition of binary numbers in two's complement with carry-save overflow correction. For the correction of overflow errors, the carry bit of the adder (AD.sub.n-2) having the second highest significance is replaced by the carry bit of the most significant adder (AD.sub.n-1) and, in case the carry bits of the two most significant adders (AD.sub.n-1, AD.sub.n-2) are unequal, the intermediate sum bit of the most significant adder (AD.sub.n-1) is replaced by the carry bit thereof. The element AD.sub.kn-1 has the same number of transistors as the other adders AD.sub.0 . . . AD.sub.n-2.