Method of fabricating an integrated circuit with metal interconnecting layers above and below active circuitry
US4889832A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 23, 1987 |
| Grant date | Dec 26, 1989 |
| Priority date | — |
| Expiry date | Dec 23, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming backside contacts includes first forming an etch stop layer (12) beneath the surface of a silicon substrate. An active circuit is then formed in the silicon surface and associated metal interconnecting layers formed on the upper surface of the substrate. A planarizing layer is then formed on the upper surface of the substrate which is operable to be connected to a mechanical support. Thereafter, the backside of the substrate is etched away up to the etch stop layer (12). The thickness of the remaining substrate between the metal layers on the upper surface and the etch stop layer is sufficiently thin that the alignment marks on the upper surface can be seen through the substrate. These alignment marks are utilized to form vias from the backside to the active elements and then deposit and pattern interconnecting layers on the backside.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.