An integrated controlled FET switch
US4890012A · kind A · utility
3Cited by
8References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 27, 1988 |
| Grant date | Dec 26, 1989 |
| Priority date | — |
| Expiry date | May 27, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/6872
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switch means designed as an integrated circuit possesses two series-connected FETs (Q1P, Q2P; Q1N, Q2N) whose common switching point (N5, N6) is clamped via a clamp FET (Q3N, Q3P) to a reference potential. The conductivity type of the clamp FET (Q3N, Q3P) is opposite the conductivity type of the two series-connected FETs (Q1P, Q2P; Q1N, Q2N). In the case of an n-channel clamp FET (Q3N), the latter is connected to negative potential. In the case of a p-channel clamp FET (Q3P), it is connected to positive potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.