CMOS-BiCMOS gate circuit
US4890017A · kind A · utility
17Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1987 |
| Grant date | Dec 26, 1989 |
| Priority date | — |
| Expiry date | Dec 1, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09448
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.