CMOS input buffer stable for the variation of a power supplying voltage
US4890051A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1988 |
| Grant date | Dec 26, 1989 |
| Priority date | — |
| Expiry date | Dec 27, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/247
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A CMOS input buffer for converting the TTL level signals to the CMOS level signals, thereby being capable of stably operating within all allowable range of the power supply voltage, is disclosed. Said CMOS input buffer includes an inverter, a reference voltage generating circuit, a power supply voltage tracer circuit and an input circuit. The input circuit includes P-channel MOS transistors and N-channel MOS transistors so as to supply a stable logic output in response to the input signal of TTL level, regardless of variation of the power supply voltage Vcc, under the control of a voltage that is approximately proportional to the difference between the reference voltage and the power supply voltage within a fixed range of the power supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.